1. Field
Embodiments of the present invention generally relate to the field of semiconductor devices. More particularly, embodiments relate to memory storage cells.
2. Background
In recent years, dual bit memory cells, such as those employing MirrorBit® technology developed by Spansion, Inc., have been developed. As the name suggests, dual bit memory cells double the intrinsic density of a flash memory array by storing two physically distinct bits on opposite sides of a memory cell. Ideally, reading or programming one side of a memory cell occurs independently of whatever data is stored on the opposite side of the cell.
FIG. 1A illustrates a conventional dual-bit memory cell 100. Conventional dual bit memory cell 100 typically includes a substrate 110 with source/drain regions 120 implanted therein, a first oxide layer 130 above the substrate 110, a continuous charge trapping layer 140, a second oxide layer 150, and a poly layer 160. The bottom oxide layer 130 is also commonly referred to as a tunnel oxide layer.
Programming of a dual bit memory cell 100 can be accomplished, for example, by hot electron injection. Hot electron injection involves applying appropriate voltage potentials to the gate, source, and drain of the cell 100 for a specified duration until the charge trapping layer 140 accumulates charge. While for simplicity, charge is typically thought of as being stored in a fixed location (i.e., the edges) of charge trapping layer 140, in reality the location of the trapped charge for each node falls under a probability curve, such as curves 170 and 175. For the purposes of this discussion the bit associated with curve 170 shall be referred to as the “normal bit” and the bit associated with curve 175 shall be referred to as the “complementary bit”. It should be appreciated from FIG. 1A that the memory cell 100 illustrated therein is reasonably large, such that the two charge storage nodes can be fairly localized and well separated.
FIG. 1B illustrates a conventional dual bit memory cell 105 having a smaller process geometry than the memory cell 100 of FIG. 1A. FIG. 1B illustrates that as the cell gets smaller, the distribution curves 170 and 175 stay the same, resulting in an overlap of the curves 170 and 175. Such an overlap in these regions can result in the contamination of one bit by its neighboring bit. This is also known as complementary bit disturb or program disturb.
FIG. 2 graphically illustrates complementary bit disturb in a conventional memory cell having a continuous charge trapping layer. FIG. 2 illustrates the example of when the normal bit has been programmed, but the complementary bit has not. In such a case, the normal bit should read “0” and the complementary bit should read “1”. Whether or not a bit is programmed is reflected by a delta in the threshold voltage associated with that bit. In conventional dual bit memory cells, programming of a normal bit also results in a shift of the Vt of the complementary bit. For example, in a memory cell having a channel length L1, changing the Vt of the normal bit by X results in a change of the Vt of the complementary bit of Y. As the cell size gets smaller, resulting in a shorter channel length (e.g., L2), the disturbance increases, even before the bits physically touch each other. Thus, conventional dual bit memory cells do not have adequate protection against physical contamination of one bit by its neighboring bit, as well as protection against program disturb in general.
Erasure of a dual bit memory cell can be accomplished using, for example, the conventional technique of “hot hole injection” (sometimes referred to as band-to-band (BTB) hot hole injection). In hot hole injection, appropriate voltages are applied to the gate and a drain, while the source is floated or grounded, to erase one of the memory cells (typically the normal bit). Conversely, the complementary bit cell is erased by floating the drain and applying the appropriate voltages to the source and the gate. With such erase conditions, a BTB tunnel current is created under the gate. Holes are generated under these conditions and accelerate from the n-type drain region into the p-type substrate. The generated holes are accelerated in the electrical field created near the P-N drain/body junction. Some of the accelerated holes surmount the oxide-to-silicon interface between the substrate and the bottom oxide and are injected into the nitride layer to displace electrons (e.g., by recombination) and erase the cell. However, as these hot holes bombard the interface between the substrate and the bottom oxide, the interface, as well as the bottom oxide, is damaged causing undesirable interface states and degraded reliability over program/erase cycling.
Another erase mechanism is channel erase, also commonly referred to as a Fowler-Nordheim (FN) erase operation. Typically, in conventional dual bit memory cells, the top and bottom oxide have the same and dielectric constant, resulting in the vertical fields during erase being the same across both the top and bottom oxides. Therefore, during an FN channel erase, electrons are pushed out from the charge restoring layer to the substrate. At the same time, more electrons flow from the N+ gate through the top oxide and get trapped in the charge storing layer. Therefore while there is a net current from the control gate to the substrate, charge is not erased effectively from the charge storing layer.
In addition to the specific issues related to dual bit memory cells, decreasing memory cell channel length in general also raises several other issues, commonly referred to as the “short channel effect.” For instance, short channel effect may refer to source/drain leakage issues, loss of gate control issues, etc.